Currently, with wider application of electronic devices, requirements on stability of circuits become much stricter. In various electronic circuits or electronic systems, it is required to provide a bias current for some circuits, such as an Analog-to-Digital Converter (ADC) circuit, a phase-locked loop (PPL) circuit and a memory circuit.
Bias current plays an essential role in an electronic circuit or an electronic system. FIG. 1 schematically illustrates a circuit for generating a bias current in existing techniques. The circuit includes a P-channel metal oxide semiconductor (PMOS) transistor P10, a PMOS transistor P11, a PMOS transistor P12, a N-channel metal oxide semiconductor (NMOS) transistor N10 and a NMOS transistor N11, where the PMOS transistors P10 and P11 constitute a first current mirror structure, the PMOS transistors P11 and P12 constitute a second current mirror structure, the NMOS transistors N10 and N11 constitute a third current mirror structure and operate in a saturation region, a drain of the PMOS transistor P10 is connected with a drain of the NMOS transistor N10 and outputs a current Iin1, a drain of the PMOS transistor P11 is connected with a drain of the NMOS transistor N11 and outputs a current Iin2, and a drain of the PMOS transistor P12 outputs a bias current Io.
Referring to FIG. 1, the circuit for generating the bias current further includes: a power-supply unit D adapted to provide a power-supply voltage for the PMOS transistors P10, P11 and P12; a grounding unit adapted to provide a grounding voltage for the NMOS transistor N10 and N11; and a resistor R which is connected with the grounding unit and the NMOS transistor N10, and arranged therebetween.
However, the circuit for generating the bias current has following disadvantages. The current Iin1, the current Iin2 and the output bias current To have proportional relations. During operation, the NMOS transistors N10 and N11 operate in the saturation region, thus, the third current mirror structure has a clamping function to the currents Iin1 and Iin2. The current Iin1 is approximately equal to the current Iin2. Assuming a ratio among the bias current Io, the current Iin1 and the current Iin2 is 1:1:1, Equation (a) is obtained as follows.Io=Iin1=Iin2=[2/μnCox(W/L)N]*(1/R2)*(1−1/√{square root over (K0)})2  (a)where μn is a migration rate of the NMOS transistor, Cox is capacitance of a gate oxide layer per unit area of the NMOS tube, (W/L)N is a width-to-length ratio of the NMOS transistor N11, and K0 is a ratio of a width-to-length ratio of the NMOS transistor N10 to the width-to-length ratio of the NMOS transistor N11.
In the Equation (a), μn and R are sensitive to temperatures, and particularly, μn is seriously sensitive to temperatures. Therefore, the output bias current To is greatly sensitive to temperatures.
In the existing techniques, a bias current generated in a circuit is sensitive to temperatures, thus, an output current may be not accurate, which may affect the stability of an electronic circuit or an electronic system.